The present disclosure relates to an image display apparatus which performs image display by driving display elements with analog voltage obtained by digital-analog conversion (hereinafter, referred to as DA conversion) for digital video signal using ramp signal or the like.
Image display apparatuses that have made a considerable progress in recent years are display panel apparatuses using liquid crystals (liquid crystal display apparatuses). The liquid crystal display apparatuses are widely used in view finders and liquid crystal display panels of video cameras, televisions for automobiles, display panels of navigation systems, displays of notebook personal computers, and the like.
The liquid crystal display apparatuses are originally configured to display analog video signal. The driver circuit of a liquid crystal display apparatus with a high resolution and a high image quality is very large in scale and requires a lot of chips. Moreover, the driver circuit needs to be highly accurate. The cost restriction of the display panel is one of major factors to determine the display quality.
In recent years, peripheral circuits are being increasingly digitalized. It is therefore convenient for the entire system that the video signal is inputted to liquid crystal elements in the form of digital data. In order to implement high image quality without increasing the circuit scale for satisfying the cost restriction, an image display apparatus is proposed, which includes a DA converter to convert digital video signal to analog video signal (refer to Japanese Unexamined Patent Application Publication No. 6-178238 (PTL 1)).
In the conventional image display apparatus described in PTL 1, the same number of video switches (analog switches) as the number of pixels per line are turned on simultaneously at the beginning of every horizontal scanning period, and a simple ramp signal with the same period as the horizontal scanning period including all video signal components from black to white is supplied to data lines through the respective analog switches.
A counter counts based on a clock with a predetermined frequency and outputs the counter value sequentially, changing from the minimum to maximum value in each horizontal scanning period.
Comparators compare digital data of the video signal displayed in each horizontal scanning period with the counter value of the counter on a pixel-by-pixel basis, and output a matching pulse when the digital data matches the counter value. The analog switches provided, corresponding to the comparators remain turned off after the matching pulse is outputted.
The level of the ramp signal, just before each analog switch is turned off, is sampled and held to be supplied to the corresponding pixel. The digital video signal is thereby converted to the analog video signal.
The liquid crystal display apparatus described in PTL 1 is configured to sample and hold predetermined voltages corresponding to digital data based on the referential ramp signal.
The liquid crystal display apparatus described in PTL 1 has an advantage of implementing high image quality without increasing in circuit scale.
However, in some pictures to be displayed, the same voltage is sampled and held at the same time for plural pixels, or some voltages are not sampled and held at all. The load on the ramp signal therefore significantly changes in many cases. Such changing load causes tonality degradation called streaking in the displayed image.
FIGS. 15A and 15B illustrate examples of an original image and a displayed image with the tonality degraded. The original image illustrated in FIG. 15A includes a 50% gray box (image 2a) and a horizontally-long box (image 3a) having the same gray level as the image 2a, which are arranged on image 1a as a black background. In FIG. 15A, the 50% gray images 2a and 3a are illustrated in white.
When digital data of the original image is inputted to the liquid crystal display apparatus, the liquid crystal display apparatus displays the image illustrated in FIG. 15B. In the display image illustrated in FIG. 15B, a gray box (image 2b) and a horizontally-long box (image 3b) which is slightly darker than the image 2b—although the image 3b originally must have the same gray level as the image 2b—are provided on image 1b as a black background.
The liquid crystal display apparatus displays the display image as illustrated in FIG. 15B because the horizontal width of the gray part in image 3b is larger than that in image 2b and the number of analog switches which are turned off at the same time in each horizontal scanning period is smaller in displaying image 3b than in displaying image 2b. 
The cause thereof is described using FIGS. 16 and 17. FIG. 16 illustrates an equivalent circuit diagram of an example of the main part of the liquid crystal display apparatus described in PTL 1. In FIG. 16, an output equivalent circuit 161 of a conversion analog signal generator includes an internal buffer of a DA converter which converts ramp signal data (digital data) to ramp signal (analog signal) and an output impedance Z0 thereof. On the output side of the conversion analog signal generator, n analog switches are connected in parallel.
Herein, the n analog switches correspond to the number of pixels arranged in the horizontal direction of the screen and are turned on at the beginning of every horizontal scanning period.
Pixel values of the digital video signal are compared with respective counter values of n counters (not illustrated) which count up from the minimum to the maximum value in each horizontal scanning period. Each counter is configured to output a matching pulse when the pixel value matches the counter value. By the matching pulse, the analog switch at the position of the pixel corresponding to the counter whose counter value matches the pixel value is turned off until the beginning of the next horizontal scanning period.
When turned off, the analog switch samples the ramp signal, which starts from the minimum gray level at the beginning of each horizontal scanning period and reaches the maximum gray level just before the end of the horizontal scanning period, and outputs the sampled ramp signal voltage to the corresponding pixel circuit.
In FIG. 16, the equivalent circuit 162 of each analog switch is represented by a series circuit of one analog switch and input impedance Z1. V0 indicates output voltage of the buffer in the DA converter which generates the ramp signal (analog signal) from the ramp signal data (digital data), and V1 indicates input voltage of the analog ramp signal which is outputted from the DA converter and is supplied to the n analog switches in common.
Herein, the input voltage V1(s) of the analog switches is expressed by Equation (1) below. In Equation (1), s is the number of analog switches which are simultaneously turned off at a certain time, and 0<=s<=n.V1(s)=[Z1/{(n−s)Z0+Z1}]V0  (1)
In the black background (image 1b) illustrated in FIG. 15B, V0=0, and the input voltage V1 of the analog switches is 0 based on Equation (1).
Herein, it is assumed that Z0=1, Z1=100, and n=256. The horizontal width of the 50% gray image 2b illustrated in FIG. 15 is 64 pixels, and the horizontal width of the 50% gray image 3b illustrated is 128 pixels. In this case, in displaying image 2b, the number s of analog switches simultaneously turned off is 192 (=256−64). In displaying image 3b, the number s of analog switches simultaneously turned off is 128 (=256−128).
The number s of analog switches turned off is also referred to as the number of off analog switches.
It is assumed that the original buffer output voltage V0 is 0.5 in displaying a 50% gray image.
Based on Equation (1), the input voltage V1(192) of the analog switches in displaying image 2b is 0.305, and the input voltage V1(128) of the analog switches in displaying image 3b is 0.219.
The images 2b and 3b, which originally must be displayed with an identical gray level, are different in horizontal width and are therefore different in number s of analog switches simultaneously turned off. This results in the difference in gray level as described above.
Moreover, in the processes of displaying images 2b and 3b, the input voltage V1 must be 0.5 (50%) but is lower than 0.5. Accordingly, images 2b and 3b have lower gray levels.
It is therefore revealed that the changes in buffer load, depending on the number s of off analog switches in each line display period (each horizontal scanning period) causes tonality degradation.
FIG. 17 is a graph illustrating changes of the input voltage V1(s) with respect to the number s of off analog switches. In the graph illustrated in FIG. 17, V0=0.5, Z0=1, and Z1=100. This graph reveals that as the number s of off analog switches increases, the input voltage V1(s) of the analog switches approaches the value indicating the original gray level to be displayed.
In order to solve the aforementioned problem, an image display apparatus described in Japanese Unexamined Patent Application Publication No. 2011-53644 (PTL 2) is configured as follows. The image display apparatus described in PTL 2 includes the same number of dummy pixels as the number of pixels in a row of the pixel section. To a signal line connected to the dummy pixels, current to charge the parasitic capacitance of the signal line due to ramp signal supplied through a ramp signal line is flown.
The image display apparatus described in PTL 2 includes at least one current detector to detect the charging current, a wire having an end connected to the point of connection between each of plural analog switches (video switches), and a ramp signal line. In the image display apparatus, plural dummy loads are provided for the respective wires, and the charging current detected by the current detectors is applied to the dummy loads.
In the image display apparatus described in PTL 2, current having the same value as the charging current flowing through the data lines connected to the analog switches turned off is flown to the dummy loads corresponding to the analog switches turned off, so that changes in current in the ramp signal line can be compensated accurately. In the image display apparatus described in PTL 2, therefore, changes in voltage in the ramp signal line can be reduced accurately.